Sony HBI-55 Data Cartridge / Yamaha UDC-01 Data Memory
The Sony HBI-55 and the technically equivalent Yamaha UDC-01 are 4 kB SRAM data cartridges. This SRAM, or static RAM, is very low power memory whose contents are preserved when the computer is off by means of a CR2032 coin cell battery.
Amongst others they are used by the internal firmware in Sony’s HB-55 and
HB-75 computers and by Yamaha’s CX5M music computer software. The Sony HB-55 and
HB-75’s firmware also add the ability to store a BASIC program on the HBI-55
using the SAVE "CAT:" and LOAD "CAT:" commands.
Memory access
The HBI-55 uses the 8255 PPI (Programmable Peripheral Interface) as a controller IC to access the memory. If this sounds familiar, that’s right; all MSX computers also contain a PPI to deal with slot selection, keyboard I/O etc. The HBI-55 has a PPI of its own to access the SRAM at I/O ports 0B0H-0B3H.
Here’s a little block diagram:
IORQ, A2-A7 A0-A1 RD/WR D0-D7
┌───────────────┐ │ │ │ │ ││││││││
│Addres decoding├─┐ │ │ │ │ ││││││││
└───────────────┘ │ │ │ │ │ ││││││││
┌─────────────────┴──┴─┴───┴─┴──┴┴┴┴┴┴┴┴─┐
│ 8255 Programmable Peripheral Interface │
└────┬┬┬┬┬┬┬┬────┬┬┬┬┬┬┬┬────┬┬┬┬┬┬┬┬────┘
C││││││││ B│└┴┴┤│││ A││││││││
││││││││ │ │││└───┐││││││││
││││││││ │ ││└───┐│││││││││
││││││││ │ │└───┐││││││││││
││││││││ │ └─┐ │││││││││││
┌─┴┴┴┴┴┴┴┴────┴─────┴──┴┴┴┴┴┴┴┴┴┴┴─┐
│ D0-D7 WE/OE CS A0-A10 │
│ 2x 2048 byte static RAM │
└──────────────────────────────────┘
Refer to the Sony HBI-55 Service Manual for a more detailed circuit diagram.
PPI interface
The PPI’s three ports and control register are set up as follows:
| I/O Port | Register | I/O | Value |
|---|---|---|---|
| 0B0H | Port A | O | Address bits 0-7 |
| 0B1H | Port B | O | bit 0-3: Address bits 8-11 bit 4-5: Address bits 12-13 (unused, keep 0) bit 6: Chip enable (1 = enable) bit 7: Output enable (1) or write enable (0) |
| 0B2H | Port C | I/O | Data read / write |
| 0B3H | Control | O | 89H: Read 80H: Write |
PPI ports A-C are interfaced to two 2K SRAM chips. Address bits 0-10 (Port A, B) and the data bits (Port C) are directly connected to the address and data lines of the SRAM chips. Port B bits 3-5 select the SRAM chip, up to eight in theory, but only two are present. Addresses ≥ 1000H can not be read from or written to. Bit 6 is a global chip enable. Bit 7 selects whether the SRAM chip outputs (OE) or stores (WE) the data.
Care must be taken to fully set up the data and address lines before flagging the chip enable bit. Especially if the chip is in write mode, changing the address LSB, address MSB or data will immediately store whichever address and data it is pointing to in-between, and likely cause unintended modifications to the memory. Similarly, make sure to clear the chip enable after the write.
The I/O direction of PPI port C is set using the control register. Output 89H to read, or 80H to write. Do not set the SRAM output enable and chip enable while PPI port C is in output mode. Doing this causes a short circuit and can damage the cartridge.
Procedure for reading
- Set control register (0B3H) to 89H to configure PPI port C for input.
- Set port A (0B0H) to the low eight address bits.
- Set port B (0B1H) to 11000000b ORed with the highest four address bits.
- Read the data value from port C (0B2H).
- Set port B (0B1H) to 10000000b ORed with the high four address bits.
In step 5 you can also just output 0 since we already got the value.
When reading multiple values, you can cycle through steps 2-4.
Procedure for writing
- Set control register (0B3H) to 80H to configure PPI port C for output.
- Set port C (0B2H) to the data value.
- Set port A (0B0H) to the low eight address bits.
- Set port B (0B1H) to 01000000b ORed with the high four address bits.
- Set port B (0B1H) to 00000000b ORed with the high four address bits.
When writing multiple values, you can cycle through steps 2-5.
Example code
Here’s an example BASIC program:
100 ' HBI55.BAS by Bjorn Lammers and Grauw 110 ' Controlling the 120 ' Sony Data Cartridge 130 ' 140 ' Writing 150 INPUT "Address";AD 160 INPUT "Data";DT 170 ' PPI Control: Set mode 0, port A & B & C output 180 OUT &HB3,&H80 190 ' PPI Port C: Set data 200 OUT &HB2,DT 210 ' PPI Port A: Address low 220 OUT &HB0,AD AND &B11111111 230 ' PPI Port B: Address high, write enable, chip enable 240 OUT &HB1,(AD\256) OR &B01000000 250 ' PPI Port B: Address high, write enable, chip disable 260 OUT &HB1,(AD\256) OR &B00000000 270 ' Reading 280 INPUT "Address";AD 290 ' PPI Control: Set mode 0, port A & B output, port C input 300 OUT &HB3,&H89 310 ' PPI Port A: Address low 320 OUT &HB0,AD AND &B11111111 330 ' PPI Port B: Address high, output enable, chip enable 340 OUT &HB1,(AD\256) OR &B11000000 350 ' PPI Port C: Read data 360 DT=INP(&HB2) 370 ' PPI Port B: Address high, output enable, chip disable 380 OUT &HB1,(AD\256) OR &B10000000 390 PRINT "Data: &H"+HEX$(DT) 400 END
Grauw